library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

--- Combinatorial Components

entity Adder_32x32 is
	Port (carry_in			: in	STD_LOGIC;							  	--- '1' if we want a carry into the adder
			Arg1				: in	STD_LOGIC_VECTOR (31 downto 0); 	--- Input for additon
			Arg2				: in	STD_LOGIC_VECTOR (31 downto 0); 	--- Input for addition
			Result			: out	STD_LOGIC_VECTOR (31 downto 0); 	--- Main 32 bits of results
			carry_out		: out	STD_LOGIC								--- 
			);
end Adder_32x32;

--- Ineffecient implementation of an adder using straightforward adders
architecture Lousy of Adder_32x32 is
begin
	process(carry_in, Arg1, Arg2)
		variable output : STD_LOGIC_VECTOR(32 downto 0);
		variable temp : STD_LOGIC_VECTOR(32 downto 0);
	begin
		if (carry_in = '1') then
			temp := '0' & X"00000001";
			output := STD_LOGIC_VECTOR(unsigned("0"&Arg1) + unsigned("0"&Arg2) + unsigned(temp));
		else
			temp := '0' & X"00000000";
			output := STD_LOGIC_VECTOR(unsigned("0"&Arg1) + unsigned("0"&Arg2) + unsigned(temp));
		end if;
		
		result <= output(31 downto 0);
		carry_out <= output(32);
	end process;
end Lousy;
